Welcome back to all my readers! Can you try to guess what has changed since the last post in my blog?
It’s been a long time but.. Yes! Just so, I started writing new contents in English. This is an opportunity for me to try to improve my English more and more and make the new articles immediately comprehensible all over the world. If you find any grammatical errors in these first posts, I would be grateful if you report them to me.
NB: Previous posts will not be immediately translated but efforts will be focused on new contents directly in English.
Spoiler on the next posts
Yesterday I was in Dublin talking with some guys about problems that can arise when the signals (one or more) cross from one clock domain to another. Given the importance of the topic, also called Clock Domain Crossing (CDC) I want to propose it in the next posts because in the past I talked only about a very simple case, where an asynchronous reset was feed into the system but there are also more complex cases like multi-bit signals (buses) that cross clock domains and different solutions exists.
The topic is important to know because regular simulations (ex. testbenches with ModelSim) usually doesn’t catch metastability problems which are therefore very difficult to detect because sporadic.
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